Cell/B.E. Hardware Structure

Cell/B.E. is a “Heterogeneous multi-core” whichi has nine different configuration cores, one PowerPC Processor Element and eight Synergistic Processor Element.
EIB(Element Interconnect Bus) connects each processor which is a high speed communication bus. The EIB also provides connections to main memory and external I/O devices, making it possible for processor cores to access data.

PPE(PowerPC Processor Element)

• Cell/B.E. incorporates one PPE.
• The PPE is responsible for running the operating system.
• I/O control when the operating system accesses the main memory and external devices.
• Coordinating the SPEs.
• PPU(PowerPC Processor Unit)
  • The PPU is the processing unit in the PPE.
  • Each 32KB L1 cache (32KB inst. cache, 32KB data cache)

SPE (Synergistic Processor Element)

• Cell/B.E. incorporates eight SPEs.
• The SPEs designed to iterate simple operations.
• SPE is a RISC processor with SIMD organization. SIMD means a computing method that enables processing of multiple data with a single instruction.
• SPU (Synergistic Processor Unit)
  • Each SPE consists of a SPU.
  • The main processing unit of SPE.
  • Contains 256KB Local Store(LS) whitch is the only memory that can be referenced directly from the SPU.
• LS (Local Store)
  • Dedicated memory of SPU
  • The only memory that can be referenced directly from the SPU.
    *SPU uses MFC when it accesses main memory and LS of other SPUs.
• MFC (Memory Flow Controller)
  • A data transfer unit that enables data transfer between an SPU and the main memory or other SPUs.
  • The SPUs send data transfer requests to the MFC via a channel interface.